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ics for consumer electronics quarter pip processor sda 9189x (a123 / a132) 4pip data sheet 03.96
edition 03.96 this edition was realized using the software system framemaker a . published by siemens ag, bereich halbleiter, marketing- kommunikation, balanstra?e 73, 81541 mnchen siemens ag 1996. all rights reserved. attention please! as far as patents or other rights of third par- ties are concerned, liability is only assumed for components, not for applications, pro- cesses and circuits implemented within com- ponents or assemblies. the information describes the type of compo- nent and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements components may contain dangerous substances. for in- formation on the types in question please contact your nearest siemens office, semi- conductor group. siemens ag is an approved cecc manufac- turer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us un- sorted or which we are not obliged to accept, we shall have to invoice you for any costs in- curred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the ex- press written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support de- vice or system, or to affect its safety or ef- fectiveness of that device or system. 2 life support devices or systems are in- tended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
sda 9189x revision history: current version: 03.96 previous version: page (in previous version) page (in new version) subjects (major changes since last revision) 26.01.1994: target specification 15 26.01.1994: not allowed display areas, display position 30 26.01.1994: character m instead of % 32 26.01.1994: bit d6 of register 0f inverted 36 26.01.1994: adjustment values vsidel 38 26.01.1994: da converter 30 08.04.1994: character & instead of ! 35; 38 08.04.1994: text subaddress 06 and 0f 38 08.04.1994: output voltage anacon 41 08.04.1994: supply voltage range 24 20.09.1994: examples for the adjustment of frame colors 32; 36 20.09.1994: new i 2 c bits vsiisq and vspisq 33 20.09.1994: notes at subaddress 00; bits d1 and d3 34 20.09.1994: note & warning at subaddress 02 35 20.09.1994: warning at subaddress 06 36 20.09.1994: warning at subaddress 07 38 20.09.1994: elimination of bit d6 of subaddress 0f 41 20.09.1994: output voltage 43 20.09.1994: remark for series resistance 46 20.09.1994: values supply current 47 20.09.1994: values dac current 49 20.09.1994: new diagram 51; 52 20.09.1994: new application circuit and layout proposal
sda 9189x table of contents page semiconductor group 4 03.96 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 display modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 input signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.1 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.2 decimation window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.3 decimation filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 pip field memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 picture sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.2 memory writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.3 memory reading and synchronization to parent channel . . . . . . . . . . . . . 22 2.4 output signal processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.1 display position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4.2 line standard of the pip picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.3 interpolation of the chrominance signals . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.4.4 framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.5 full screen background insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.6 filling pip picture with color . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.7 wipe-in/wipe-out facility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.8 output formats and rgb conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.9 matrix equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.10 select signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.11 blanking signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.4.12 pedestal for the chrominance signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 digital-to-analog conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5.1 analog video outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.5.2 analog control signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6 on-screen display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6.1 display format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6.2 character programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.6.3 character and character background luminance . . . . . . . . . . . . . . . . . . . . 28 2.6.4 character set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.7 numerical pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8.1 i 2 c bus addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8.2 i 2 c bus receiver format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.8.3 i 2 c bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
sda 9189x table of contents page semiconductor group 5 03.96 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3.2 operational range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3.3 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4 diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.1 output current of da converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.2 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2.1 application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 4.2.2 application board layout proposal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4.3 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4.3.1 phase relation of sync pulses at frame mode . . . . . . . . . . . . . . . . . . . . . . 52 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 i 2 c bus purchase of siemens i 2 c components conveys the license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips.
sda 9189x semiconductor group 6 03.96 1 general description the picture insertion processor sda 9189x generates a reduced size picture of an inset video channel for the purpose of combining it with another video signal (parent channel). the easy implementation of the ic into an existing system needs only a few additional external components. there is a great variety of application facilities in consumer and professional products (tv sets, vcrs, supervising monitors, multi-media, etc.).
p-dso-32-2 semiconductor group 7 03.96 quarter pip processor sda 9189x data sheet type ordering code package sda 9189x Q67100-H5148 p-dso-32-2 1.1 features ? high system integration filtering, field memory, rgb-matrix, da-conversion, clock generation, and control circuits integrated on one chip ? 4 picture sizes 1/4th, 1/9th, 1/16th, or 1/36th of normal size ? high resolution display 13.5 mhz/27 mhz display clock frequency 288 luminance and 72 chrominance pixels per inset line for picture size 1/4 6-bit amplitude resolution for each incoming signal component frame mode display in single-pip modes horizontal and vertical filtering special antialias filtering for the luminance signal ? single and multi pip display up to 9 pictures of 1/36th size (8 still and 1 moving) up to 4 pictures of 1/16th size (3 still and 1 moving) up to 2 pictures of 1/9th size (1 still and 1 moving) up to 3 pictures of 1/9th size (2 still and 1 moving) as pop display in 16:9 tv sets (in multi-pip modes only field mode display possible) ? multistandard applications automatic recognition of 625 lines/525 lines standard (inset and parent channel) scan conversion systems as flickerfree display systems (parent channel) ? hdtv (parent channel) ? 16:9 compatibility operation in 4:3 and 16:9 tv sets 4:3 inset signals on 16:9 displays (picture size 1/4 and 1/9) 16:9 inset signals on 4:3 displays (picture size 1/9 and 1/16)
sda 9189x semiconductor group 8 03.96 ? digital inputs y, + (b-y), + (r-y) compatible with triple adc sda 9187-2x ? analog outputs y, + (b-y), + (b-y) or y, C (b-y), C (b-y) or rgb 3 rgb-matrices: ebu, ntsc (japan), ntsc (usa) ? digital to analog converter output e.g. for color decoder adjustment 6-bit resolution ? freely programmable position of inset picture steps of 1 pixel and 1 line all pip and pop positions are possible inside the standard display area ? programmable framing 4096 frame colors variable frame width ? full screen background insertion 64 background colors or transparent display (parent picture seen) ? wipe-in/wipe-out facility start and end of insertion is the lower right pip corner 4 periods programmable ? freeze picture ? i 2 c bus control ? up to three ics in one application three different i 2 c bus addresses up to 3 moving pictures using 3 ics up to 27 pictures of 1/36th size ? on-screen display of channel index 64 characters programmable (alphanumeric and special symbols) 5 characters displayed in every pip picture 4 different character luminance values (b-y = r-y = 0) 4 background luminance values (b-y = r-y = 0) or transparent mode (inset picture seen) ? numerical display pll circuit for high stability clock generation ? no necessity of pal/secam delay lines when using suitable color decoders ? p-dso-32 package/350 mil (smd) ? 5 v supply voltage
sda 9189x semiconductor group 9 03.96 1.2 pin configuration (top view) figure 1 p-dso-32-2
sda 9189x semiconductor group 10 03.96 1.3 pin definitions and functions pin no. symbol function 1) descriptions 1 vsi i/ttl inset vertical sync input 2 xin i pll quartz oscillator input 3 xq q pll quartz oscillator output 4 adr i 3-l i 2 c address 5 v ref i/ana dacs reference voltage 6 v dda s dacs and pll positive voltage supply 7 v ss s digital ground 8 out1 q/ana analog output r or + (r-y) or C (r-y) 9 out2 q/ana analog output g or y 10 out3 q/ana analog output b or + (b-y) or C (b-y) 11 anacon q/ana analog output (e.g. color decoder adjustment) 12 v ssa s dacs and pll ground 13 v dd s digital positive voltage supply 14 sel q/var signals out1 - out3 valid 15 hsp i/ttl parent horizontal sync input 16 vsp i/ttl parent vertical sync input 17 sda iq/ttl i 2 c data input/output 18 scl i/ttl i 2 c clock 19 v ss s digital ground 20 ll3i i/ttl line locked clock inset picture 21 uvin0 i/ttl digital uv input data 22 uvin1 i/ttl digital uv input data 23 uvin2 i/ttl digital uv input data 24 uvin3 i/ttl digital uv input data 1) s: supply, i: input, q: output, ttl: digital (ttl), ana: analog, 3-l: 3 level signal, var: variable configuration of output stage (open source, open drain, ttl)
sda 9189x semiconductor group 11 03.96 25 yin0 i/ttl digital y input data 26 yin1 i/ttl digital y input data 27 yin2 i/ttl digital y input data 28 yin3 i/ttl digital y input data 29 yin4 i/ttl digital y input data 30 yin5 i/ttl digital y input data 31 v dd s digital positive voltage supply 32 hsi i/ttl inset horizontal sync input 1) s: supply, i: input, q: output, ttl: digital (ttl), ana: analog, 3-l: 3 level signal, var: variable configuration of output stage (open source, open drain, ttl) 1.3 pin definitions and functions (contd) pin no. symbol function 1) descriptions
sda 9189x semiconductor group 12 03.96 1.4 functional block diagram figure 2
sda 9189x semiconductor group 13 03.96 2 system description 2.1 display modes 8 single- and 10 multi-pip display modes are available. decimation, memory controlling, framing and on-screen display insertion depend on the selected display mode (pipmod). in the multi-pip modes the complete inset picture can contain up to 9 partial pictures (see diagrams below). one of the partial pictures shows a moving picture, whereas the others show still pictures. the partial picture that has to be written is addressed via i 2 c bus. the addresses (wrpos) for the individual pictures are shown in the diagrams. the same addresses serve to choose the position of the moving picture. the multi-pip modes allow tuner scanning. four display modes are provided for applications with 16:9 inset signals or displays (see table 1 ). the single-pip display modes 15 and 18 can be used to display 4:3 inset signals on 16:9 displays. to show 16:9 inset signals on 4:3 displays the single-pip display modes 16 and 19 have been added. by means of multi-pip display mode 17 a pop picture on a 16:9 display can be created. if a display mode is chosen that is not realized (modes 9, 12, and 20 to 31), the pip insertion is switched off automatically (pipon = 0). table 1 display mode (pipmod) picture size, picture configuration 0 (00000) 1 1/4 1 (00001) 1 1/9 2 (00010) 1 1/16 3 (00011) 1 1/36 4 (00100) 4 1/16, 2 rows of 2 pictures 5 (00101) 4 1/16, side by side 6 (00110) 4 1/16, one upon another 7 (00111) 9 1/36, 3 rows of 3 pictures 8 (01000) 2 1/9, side by side 9 (01001) not realized (pipon = 0) 10 (01010) 8 1/36, 2 rows of 4 pictures 11 (01011) 2 1/9, one upon another 12 (01100) not realized (pipon = 0) 13 (01101) 8 1/36, 2 columns of 4 pictures one upon another
sda 9189x semiconductor group 14 03.96 the following diagrams show the various display modes. the figures on top of the rectangles give the width of the complete inset picture in pixels whereas the figures on the right specify its height by the number of lines. the values for the multi-pip display modes are obtained by adding the widths and heights of the partial pictures. the sizes of the partial pictures correspond to the sizes of the inset pictures of the single-pip modes (see below). 14 (01110) 4 1/36, 2 rows of 2 pictures 15 (01111) 1 1/9, 4:3 inset signal on 16:9 display horizontal decimation 4:1, vertical decimation 3:1 16 (10000) 1 1/16, 16:9 inset signal on 4:3 display horizontal decimation 3:1, vertical decimation 4:1 17 (10001) 3 1/9, 4:3 inset signals on 16:9 display horizontal decimation 4:1, vertical decimation 3:1 one upon another 18 (10010) 1 1/4, 4:3 inset signal on 16:9 display horizontal decimation 3:1, vertical decimation 2:1 19 (10011) 1 1/9, 16:9 inset signal on 4:3 display horizontal decimation 2:1, vertical decimation 3:1 20 (10100) : 31 (11111) not realized (pipon = 0) table 1 (contd) display mode (pipmod) picture size, picture configuration
sda 9189x semiconductor group 15 03.96 figure 3 mode 5 mode 4 mode 2 mode 0 288 126 (102) 576 63 (51) mode 3 mode 1 0 0 0 0 01 23 0123 144 63 (51) 42 (34) 126 (102) 84 (68) 192 96 288
sda 9189x semiconductor group 16 03.96 figure 4 the display modes 9 and 12 are not realized. for a pip display line standard of 525 lines the values in parenthesis are valid. 144 252 (204) mode 6 mode 7 mode 8 mode 10 mode 11 mode 13 384 84 (68) 192 168 (136) 192 168 (136) 64 (68) 384 288 126 (102) 0 1 2 3 012 345 678 01 0123 4567 0 1 01 23 45 67
sda 9189x semiconductor group 17 03.96 figure 5 192 84 (68) mode 14 144 84 (68) mode 15 mode 16 192 63 (51) 144 252 (204) mode 17 192 126 (102) mode 18 84 (68) 288 mode 19 01 23 0 0 0 1 2 0 0
sda 9189x semiconductor group 18 03.96 figure 6 multi-pop feature at 16:9 application with display mode 7 and osd main picture and one pop picture live, all other pictures still figure 7 multi-pip feature with display mode 7 main picture and one pip picture live, all other pictures still 1 3 zdf - 2 ard - 4 rtl - 1 ndr - 7 hr - 2 ard - 3 zdf - 5 sfb - 6 orf - 8 ntv - 4 rtl - 9 dfs -
sda 9189x semiconductor group 19 03.96 2.2 input signal processing 2.2.1 data transfer the inset video signal is accepted as digital luminance and chrominance components with a 13.5 mhz clock for the luminance signal and a 3.375 mhz clock for the chrominance signals. inset synchronization is done via pin hsi for horizontal and pin vsi for vertical synchronization. by analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. for applications with fixed line standard (625 lines or 525 lines) the automatic detection can be switched off. the phase of the vertical sync pulse is programmable (vsidel) (see chapter 4.3 ). this way a correct detection of the field number is possible, an important condition for frame mode display. 2.2.2 decimation window a window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. the window has a width of 576 pixels for the luminance signal and a width of 144 pixels for the chrominance signals. in the vertical direction the window consists of 252 or 204 lines depending on the line standard (625 or 525 lines respectively). the horizontal position of this decimation window can be adapted to various applications with the help of a programmable delay of the luminance signal (hsidel) relative to the horizontal synchronization pulses. for hsidel = 0 the decimation window is opened 0 clock periods (13.5 mhz) after the horizontal synchronization pulse. for the 625 lines standard the 42th video line is the first decimated line, for the 525 lines standard decimation starts in the 38th video line.
sda 9189x semiconductor group 20 03.96 2.2.3 decimation filters the input signal is decimated by subsampling with horizontal and vertical filtering. a special antialias filter improves the frequency response of the luminance channel. the following decimation filters are implemented: the realized chrominance filtering allows omitting the color decoder delay line for pal and secam demodulation if the color decoder supplies the same output voltages independent of the kind of operation. in case of secam signals an amplification of the chrominance signals by a factor of 2 is necessary because there is a signal only in every second line. this chrominance amplification is programmable via i 2 c bus (amsec). horizontal decimation luminance filter chrominance filter 2:1 { 1 1 } { 1 1 } 3:1 { 1 1 1 } { 1 2 1 } 4:1 { 1 1 1 1 } { 1 1 1 1 } 6:1 { 1 1 1 1 1 1 } { 1 1 2 2 1 1 } vertical decimation luminance filter chrominance filter 2:1 { 1 1 } { 1 1 } 3:1 { 1 1 1 } { 1 2 1 } 4:1 { 1 1 1 1 } { 1 1 1 1 } 6:1 { 1 1 1 1 1 1 } { 1 1 2 2 1 1 }
sda 9189x semiconductor group 21 03.96 2.3 pip field memory the on-chip memory has a capacity of 329184 bits. it stores one decimated field of the inset picture. in the multi-pip display modes the memory is able to store one decimated field of every partial picture (e.g. during tuner scanning). 2.3.1 picture sizes the picture size depends on the horizontal and vertical decimation factors. 2.3.2 memory writing to get equal clock frequencies for luminance and chrominance signals a multiplexer at the memory input generates a 3-bit data format for both chrominance components. in field mode display only every second inset field is written into the memory, in frame mode display the memory is written continuously. data are written with the lower inset clock frequency depending on the horizontal decimation factor (6.75 mhz, 4.5 mhz, 3.375 mhz, or 2.25 mhz). memory writing can be stopped by program (freeze), a freeze picture display results (one field). in single-pip display modes frame mode display is possible having no scan conversion and the same number of lines in inset and parent channel (625 lines or 525 lines both). the result is a higher vertical and temporal resolution because of displaying every incoming field. the standards are analyzed internally and an activated frame mode display is switched to field mode display automatically when the described restrictions are no longer valid. horizontal decimation pixels/line 2:1 288 3:1 192 4:1 144 6:1 96 vertical decimation lines/field (625 lines standard) lines/field (525 lines standard) 2:1 126 102 3:1 84 68 4:1 63 51 6:1 42 34
sda 9189x semiconductor group 22 03.96 2.3.3 memory reading and synchronization to parent channel the reading frequency is normally 13.5 mhz and 27 mhz for scan conversion systems. for progressive scan conversion systems and hdtv displays a line doubling mode is available (linedbl). every line of the inset picture is read twice. synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals. these signals are fed to the ic at pin hsp for horizontal synchronization and at pin vsp for vertical synchronization. a numerical pll circuit generates a clock signal that is locked to the horizontal synchronization pulses of the parent channel. the burst gate of the sandcastle signal can be used for horizontal synchronization. a field number detection is carried out for the inset channel as well as for the parent channel. depending on the phase difference between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter. 2.4 output signal processing 2.4.1 display position the display position of the inset picture is freely programmable (poshor, posver). the first possible picture position (without frame) is 55 clock periods (13.5 mhz or 27 mhz) after the horizontal and 7 lines after the vertical synchronization pulses. starting at this position the picture can be moved over the whole display area. even pop positions (picture outside picture) can be used. note: display without disturbances is only possible if the complete pip picture is inside the visible area of the picture tube poshor < 1 poshor < 864 C 2 frwidh C psh C 42 posver < 262 C 2 frwidv C psv C 8 (60 hz mode) or posver < 312 C 2 frwidv C psv C 8 (50 hz mode) pos = picture position (see i 2 c bus) frwid. = frame width (see i 2 c bus) psh = picture size horizontal (number of pixels) psv = picture size vertical (number of line)
sda 9189x semiconductor group 23 03.96 2.4.2 line standard of the pip picture the line standard used to display the complete pip picture is programmable via i 2 c bus (piplin). the line standard of the parent channel or the inset channel can be used. in addition a fixed line standard of 625 or 525 lines can be chosen. combinations of different line standards of the inset signal and the pip display are handled in a special way: pip display 625 lines, inset signal 525 lines C the inset picture is shifted down by 12, 8, 6, or 4 lines according to picture size. due to this shift the centres of the inset pictures have the same position for both line standards. the remaining 12, 8, 6, or 4 lines at the top and the bottom of the inset picture are filled with the luminance value of the full screen background color (bcky). the chrominance values are set to 0 for these parts of the inset picture. pip display 525 lines, inset signal 625 lines C the inset picture is reduced to 102, 68, 51, or 34 lines. depending on the number of lines the first and the last 12, 8, 6, or 4 lines are omitted. in this way the display shows the centre part of the original picture. displaying multi-pip pictures this procedure is applied individually to each of the partial pictures. 2.4.3 interpolation of the chrominance signals at the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sampling rate.
sda 9189x semiconductor group 24 03.96 2.4.4 framing in this part of the circuit a colored frame is added to the inset picture. 4096 frame colors are programmable, 4 bits for each component y, (b-y), (r-y). the horizontal and vertical widths of the frame are independently programmable. in the multi-pip modes the various partial pictures are separated by inner frame elements. these parts of the frame have a fixed horizontal width of 4 pixels and a fixed vertical width of 2 lines. for infr = 0 the inner frame elements are not inserted. the outer frame elements border on the inset picture without limiting its size whereas the inner frame elements reduce the areas of the partial pictures. 2.4.5 full screen background insertion instead of showing the parent picture it is possible to fill the background (full screen picture without inset picture and its frame, bckon = 1) with a programmable color. for bckfr = 1 the background color is identical with the frame color, otherwise it is defined by 6 bits programmable via i 2 c bus: two bits for each component. the bits for the chrominance signals are used directly as msbs of the output words b-y and r-y. the remaining lsbs are set to 0. therefore 16 different colors are possible. the two bits for the y-signal choose a luminance value according to the following table (100 ire corresponds to the full scale range of dac input = integer value 63): examples for the adjustment of frame colors frame color fry d3 d0 of subaddress 09 fru d3 d0 of subaddress 0a frv d7 d4 of subaddress 0a blue 0100 0110 1010 green 0100 1000 1010 white 1100 0000 0000 red 0100 1000 0111 yellow 1100 1000 0100 cyan 1100 0010 1010 magenta 0100 0110 0100 background luminance ire integer value 0 0 20 12 0 1 30 19 1 0 40 25 1 1 50 31
sda 9189x semiconductor group 25 03.96 2.4.6 filling pip picture with color the whole inset picture can be filled with the frame color (frcol = 1) or the luminance value for the full screen background insertion without colors (bckcol = 1, frcol = 0). the frame elements remain visible. filling the pip picture with background is especially useful before starting a tuner scanning cycle. 2.4.7 wipe-in/wipe-out facility with the wipe-in/wipe-out function it is possible to make appear or disappear the complete inset picture starting or ending at the lower right corner of the inset picture position. thereby the size of the picture is continuously increased and decreased respectively. during this procedure the frame is shown with its chosen widths. 4 different periods are programmable via i 2 c bus. 2.4.8 output formats and rgb conversion different output formats are available: luminance signal y with inverted or non-inverted chrominance signals (b-y), (r-y) or rgb signals. for the rgb conversion 3 matrices are provided: matrix selection is done via i 2 c bus. the matrices are designed for the following voltages at the inputs of the adc converter (the values correspond to 100 % white and 75 % color saturation): standard amplitudes angles b-y r-y g-y b-y r-y g-y ebu 1 0.558 0.345 0 90 237 ntsc (japan) 1 0.783 0.31 0 95 240 ntsc (usa) 1 1.013 0.305 0 104 252 component input voltage (without sync) in % of full scale input range of adc y75 b-y 100 r-y 100
sda 9189x semiconductor group 26 03.96 2.4.9 matrix equations ebu ntsc (japan) ntsc (usa) 2.4.10 select signal for controlling an external fast switch (for example an rgb processor) a select signal sel is supplied. the delay of this signal relative to the luminance and chrominance components is programmable for adaption to different external output signal r g b 101 0.25 C 0.78125 1 0.1875 C 0.40625 C 1 by C ry C y = r g b 101 0.0625 C 1.09375 1 0.15625 C 0.375 C 1 by C ry C y = r g b 101 0.25 C 1.375 1 0.09375 C 0.40625 C 1 by C ry C y =
sda 9189x semiconductor group 27 03.96 processings. three different characteristics of the output stage of this signal are available. an open source, an open drain, or a ttl output can be selected via i 2 c bus (selmod). 2.4.11 blanking signals in case of full screen background insertion the circuit has to generate output signals with correctly positioned line blanking intervals relative to the horizontal synchronization pulses of the parent channel. this can be achieved by a programmable delay (blkdel). a field-blanking interval with a length of 16 lines is also provided. it is triggered by the vertical synchronization pulse of the parent channel (vsp). the generation of this field-blanking signal can be activated via i 2 c bus (verblk = 1). 2.4.12 pedestal for the chrominance signals both components of the chrominance signal are equipped with a programmable pedestal (white balance, pedestu, pedestv). the pedestal values are fed to the digital to analog converters during the line blanking intervals. for each component a 4-bit value in 2s complement code is defined via i 2 c bus. building up the 6-bit input words of the digital to analog converters these 4 bits are used as lsbs. the missing two msbs are complemented by sign extension. in this way pedestal values from C 8 to + 7 lsbs of the digital to analog converters can be achieved. 2.5 digital-to-analog conversion 2.5.1 analog video outputs the ic includes three 6-bit digital to analog converters for the video outputs. each converter supplies a current through an external resistor that is placed between v ssa and out1, out2, out3 respectively. the current is controlled by a digital control circuit. 2.5.2 analog control signal the additional 6-bit digital to analog converter that provides an analog control signal (e.g. for color decoder adjustment) is fed directly by a 6-bit signal programmable via i 2 c bus. no external resistor is needed at output anacon. 2.6 on-screen display 2.6.1 display format the on-screen display allows to insert a block of 5 characters into each of the pip pictures. the characters are placed in a box (background) with a width of 64 pixels and a height of 12 lines. this box is situated in the upper left corner of the pip pictures. the
sda 9189x semiconductor group 28 03.96 background box can be made transparent (charbck = 0), i.e. behind the characters the inset picture becomes visible. 64 different characters are stored in a character rom (see table 2 ). each character is defined by a pixel matrix consisting of 10 lines and 12 pixels per line. 2.6.2 character programming the 5 characters per block are programmable via i 2 c bus using a 7-bit code which is identical with the ascii code except for some of the special characters. the codes are placed in a character ram consisting of 45 cells. the size of the ram is determined by the number of characters per block (5) and the maximum number of pip pictures (9 in multi-pip display modes). the character codes can be transmitted in two ways: each of the 45 ram locations can be reached separately by its 7-bit address or the ram can be written consecutively starting at an arbitrarily chosen position. in this case the ram address is increased automatically. the 7-bit address consists of two parts: the 4 msbs are used to choose one of the partial pictures and the 3 lsbs to select one of the 5 characters per block.
sda 9189x semiconductor group 29 03.96 2.6.3 character and character background luminance the chrominance components of the characters and their background box always have the value 0. the luminance values are programmable via i 2 c bus according to the following tables (100 ire corresponds to the full scale range of dac input = integer value 63): table 2 ire integer value character luminance 0 0 60 38 0 1 70 44 1 0 80 50 1 1 90 56 character background luminance 0 0 10 6 0 1 20 12 1 0 30 19 1 1 40 25
sda 9189x semiconductor group 30 03.96 2.6.4 character set figure 8 this figure shows the pixel matrices of the characters stored in the character rom. 1011010=5a 1011110=5e 1011111=5f 0001010=0a 0100000=20 0100001=21 0100100=24 0100101=25 0001011=0b 0101010=2a 0101011=2b 0101101=2d 0110000=30 0110001=31 0110010=32 0110011=33 0110100=34 0110101=35 0101111=2f 0110110=36 0111000=38 0111001=39 0111100=3c 0111101=3d 0110111=37 0111110=3e 1000001=41 1000010=42 1000011=43 1000100=44 1000101=45 1000110=46 0111111=3f 1000111=47 1001001=49 1001010=4a 1001011=4b 1001100=4c 1001101=4d 1001110=4e 1001000=48 1001111=4f 1010001=51 1010010=52 1010100=54 1010101=55 1010110=56 1010000=50 1010111=57 1011001=59 1011101=5d 1011000=58 1011011=5b 1010011=53 0100011=23 0000001=01 0000010=02 0000011=03 0000100=04 0000101=05 0000110=06 0001000=08 0001001=09 0000111=07
sda 9189x semiconductor group 31 03.96 2.7 numerical pll a numerical pll circuit supplies a clock of about 27 mhz with high stability. the nominal quartz frequency is 20.48 mhz. the generated clock is locked to the parent horizontal synchronization pulses. its frequency varies with the frequency of this signal. four different characteristics of the pll behavior can be chosen to handle synchronization signals from various sources (plltc). if the pll is switched off an external 13.5 or 27 mhz parent line locked clock can be fed to the ic. using up to three sda 9189x ics in the same application only one quartz is necessary. note: before setting bit d3 of subaddress 00 (read27) noise reduction of the vsp pulse must be switched off (d5 of subaddress 08 = 1). 2.8 i 2 c bus 2.8.1 i 2 c bus addresses three different i 2 c bus addresses are programmable via pin adr. 2.8.2 i 2 c bus receiver format s: start condition a: acknowledge p: stop condition only write operation is possible. an automatical address increment function is implemented. pin adr address (bin) address (hex) low level ( v ss or v ssa ) 1 1 0 1 0 1 1 d6 mid level (open) 1 1 0 1 1 1 0 dc high level ( v dd or v dda ) 1 1 0 1 1 1 1 de s address 0 a subaddress a data byte a *** a p
sda 9189x semiconductor group 32 03.96 2.8.3 i 2 c bus commands overview after switching on the ic the data bytes of all registers are set to 0, the bit plloff is set to 1 . sub add. (hex.) data byte d7 d6 d5 d4 d3 d2 d1 d0 00 0 0 freeze plloff read27 linedbl frame pipon 01 0 seldel3 seldel2 seldel1 seldel0 verblk poshor9 poshor8 02 poshor7 poshor6 poshor5 poshor4 poshor3 poshor2 poshor1 poshor0 03 posver7 posver6 posver5 posver4 posver3 posver2 posver1 posver0 04 0 piplin1 piplin0 pipmod4 pipmod3 pipmod2 pipmod1 pipmod0 05 wrpos3 wrpos2 wrpos1 wrpos0 pmod1 pmod0 imod1 imod0 06 0 0 bckcol hsidel4 hsidel3 hsidel2 hsidel1 hsidel0 07 amsec 0 vsiisq vsidel4 vsidel3 vsidel2 vsidel1 vsidel0 08 0 0 vspisq vspdel4 vspdel3 vspdel2 vspdel1 vspdel0 09 con3 con2 con1 con0 fry5 fry4 fry3 fry2 0a frv5 frv4 frv3 frv2 fru5 fru4 fru3 fru2 0b infr selmod1 selmod0 frwidv1 frwidv0 frwidh2 frwidh1 frwidh0 0c 0 0 0 0 mat1 mat0 chrpip outfor 0d 0 plltc1 plltc0 00000 0e pedestv3 pedestv2 pedestv1 pedestv0 pedestu3 pedestu2 pedestu1 pedestu0 0f daconst 0 ancon5 ancon4 ancon3 ancon2 ancon1 ancon0 10 bckfr bcky1 bcky0 bcku5 bcku4 bckv5 bckv4 bckon 11 wipeon wipesp1 wipesp0 blkdel3 blkdel2 blkdel1 blkdel0 frcol 12 0 chary1 chary0 chbcky1 chbcky0 charbck charres osdon 13 0 charloc6 charloc5 charloc4 charloc3 charloc2 charloc1 charloc0 14 0 char6 char5 char4 char3 char2 char1 char0
sda 9189x semiconductor group 33 03.96 detailed description bit name function subaddress 00 d5 freeze 0: moving picture 1: freeze picture d4 plloff 0: internal pll on 1: internal pll off (external clock generation) d3 read27 0: pip display with single-read frequency (13.5 mhz) 1: pip display with double read frequency (27 mhz) (see note page 31 ) d2 linedbl 0: each line of the pip memory is read once (normal operation) 1: each line of the pip memory is read twice (line doubling for progressive scan conversion systems in parent channel) d1 frame 0: field mode display 1: frame mode display (if possible). correct adjustment of bits vsidel, vspdel required (see chapter 4.3 ). d0 pipon 0: pip insertion off 1: pip insertion on subaddress 01 d6 d3 seldel delay of output signal at pin sel ( C8+7 periods of read frequency clock, programmable in 2s complement code) d2 verblk 0: clamping level at dac outputs only during line blanking intervals 1: clamping level at dac outputs during line blanking intervals and field-blanking intervals (16 complete lines following the vertical synchronization pulse of the parent channel) d1 d0 poshor 2 msbs of poshor (see subaddress 02 on page 34 )
sda 9189x semiconductor group 34 03.96 subaddress 02 d7 d0 poshor horizontal position of pip picture (in steps of 1 pixel) note: the 2 msbs of poshor are located at subaddress 01, bits d0 and d1. warning: positions outside the active area of the parent picture are possible. allowed area see at chapter 2.4.1 . to avoid horizontal jumping of the picture by changing poshor from 00 1111 1111 to 01 0000 0000 its necessary to transfer the bits of both subaddresses during the same field period. subaddress 03 d7 d0 posver vertical position of pip picture (in steps of 1 line) warning: positions outside the active area of the parent picture are possible. allowed area see at chapter 2.4.1 subaddress 04 d6 d5 piplin 00: pip display line standard according to parent signal 01: pip display line standard according to inset signal 10: fixed pip display line standard: 625 lines 11: fixed pip display line standard: 525 lines d4 d0 pipmod display mode (8 single- and 10 multi-pip display modes are available, see diagrams above) detailed description (contd) bit name function
sda 9189x semiconductor group 35 03.96 subaddress 05 d7 d4 wrpos multi-pip diplay modes: selection of partial picture for writing (position number depends on the chosen display mode, see diagrams). at single-pip display modes wrpos must be set to 0000. d3 d2 pmod 00: automatic detection of line standard (parent signal) 01: fixed adjustment 625 lines 10: fixed adjustment 525 lines 11: freeze last line standard d1 d0 imod 00: automatic detection of line standard (inset signal) 01: fixed adjustment 625 lines 10: fixed adjustment 525 lines 11: freeze last line standard subaddress 06 d5 bckcol 0: inset pictures visible (normal mode) 1: pip picture filled with luminance value of the background color bcky (see subaddress 10 on page 38 ). the chrominance components are set to 0. d4 d0 hsidel delay of the horizontal synchronization pulse of the inset signal (in steps of 4 periods of 13.5 mhz clock) for the purpose of shifting the decimated part of a line. warning: adjustment of hsidel will influence the adjustment of vsidel (subaddr. 07) (see chapter 4.3 ). detailed description (contd) bit name function
sda 9189x semiconductor group 36 03.96 subaddress 07 d7 amsec 0: unity amplification of decimation filters (normal mode) 1: amplification by a factor of 2 (secam signals without delay line in the chroma decoder) d5 vsiisq noise reduction of the vsi pulse (should be set to 0 under normal conditions) d4 d0 vsidel delay of vertical synchronization pulse of the inset signal (in steps of 32 periods of 13.5 mhz clock) warning: correct adjustment value is influenced by the adjustment of hsidel (subaddr. 06; see chapter 4.3 ). subaddress 08 d5 vspisq noise reduction of the vsp pulse (should be set to 0 under normal conditions) in case changing from standard mode to line or frame conversion modes, 1 should be set during the changement of line frequency. d4 d0 vspdel delay of vertical synchronization pulse of the parent signal (in steps of 32 periods of the read clock with a frequency of 13.5 or 27 mhz) subaddress 09 d7 d4 con contrast adjustment of pip picture (16 steps) d3 d0 fry luminance component of frame color (4 msbs of 6 bits) subaddress 0a d7 d4 frv chrominance component (r-y) of frame color (4 msbs of 6 bits) d3 d0 fru chrominance component (b-y) of frame color (4 msbs of 6 bits) detailed description (contd) bit name function
sda 9189x semiconductor group 37 03.96 subaddress 0b d7 infr 0: inner frame elements off 1: inner frame elements on d6 d5 selmod 00: ttl output 01: open source output 10: open drain output d4 d3 frwidv vertical width of pip frame (0 3 lines) d2 d0 frwidh horizontal width of pip frame (0 7 pixels) subaddress 0c d3 mat1 0: ntsc rgb matrix (usa) 1: ntsc rbg matrix (japan) d2 mat0 0: ebu rgb matrix 1: ntsc rgb matrix d1 chrpip 0: non-inverted chrominance output signals + (b-y), + (r-y) 1: inverted chrominance output signals C (b-y), C (r-y) d0 outfor 0: format of output signals: y, (b-y), (r-y) 1: format of output signals: r g b subaddress 0d d6 d5 plltc 00: pll loop filter: medium damping, low res. frequency 01: pll loop filter: low damping, high res. frequency 10: pll loop filter: high damping, low res. frequency 11: pll loop filter: medium damping, high res. frequency note: after power on plltc must remain at 00 until system is locked. detailed description (contd) bit name function
sda 9189x semiconductor group 38 03.96 subaddress 0e d7 d4 pedestv 4-bit pedestal value for chrominance component (r-y) fed to corresponding dac during line-blanking interval (2s complement code, C 8 to + 7 lsbs of dac) d3 d0 pedestu 4-bit pedestal value for chrominance component (b-y) fed to corresponding dac during line blanking interval (2s complement code, C 8 to + 7 lsbs of dac) subaddress 0f d7 daconst changing from 0 to 1 starts automatic adjustment of out1 3 output current. d5 d0 ancon digital input value for dac at output pin anacon (2s complement code, all bits 0 = medium output voltage) subaddress 10 d7 bckfr 0: color of full screen background insertion according to the settings of bcky, bcku, and bckv 1: color of full screen background insertion identical with the frame color d6 d5 bcky 00: luminance value of full screen background: 20 ire 01: luminance value of full screen background: 30 ire 10: luminance value of full screen background: 40 ire 11: luminance value of full screen background: 50 ire d4 d3 bcku 2 msbs of chrominance component (b-y) of full screen background (remaining bits = 0) d2 d1 bckv 2 msbs of chrominance component (r-y) of full screen background (remaining bits = 0) d0 bckon 0: full screen background insertion off 1: full screen background insertion on detailed description (contd) bit name function
sda 9189x semiconductor group 39 03.96 subaddress 11 d7 wipeon 0: wipe-in/-out function off 1: wipe-in/-out function on d6 d5 wipesp period for opening and closing the pip window 4 values from 1/3 to 4/3 of a second can be selected (wipesp = 00 corresponds to the shortest time period) d4 d1 blkdel delay to adjust line blanking interval (parent channel, full background insertion) in steps of 8 periods of 13.5 mhz/27 mhz clock d0 frcol 0: inset pictures visible (normal mode) 1: pip picture filled with frame color subaddress 12 d6 d5 chary 00: luminance value of character 60 ire 01: luminance value of character 70 ire 10: luminance value of character 80 ire 11: luminance value of character 90 ire d4 d3 charbcky 00: luminance value of character background: 10 ire 01: luminance value of character background: 20 ire 10: luminance value of character background: 30 ire 11: luminance value of character background: 40 ire d2 charbck 0: character background insertion off 1: character background insertion on d1 charres 0: characters unchanged 1: all characters set to special character blank d0 osdon 0: on screen display of characters off 1: on screen display of characters on detailed description (contd) bit name function
sda 9189x semiconductor group 40 03.96 subaddress 13 d6 d0 charloc 7-bit address of character ram: 4 msbs address partial pictures (0 to 8 max.), 3 lsbs address character position in block (0 to 4, from left to right) subaddress 14 d6 d0 char character code to select 1 of 64 available characters detailed description (contd) bit name function
sda 9189x semiconductor group 41 03.96 3 electrical characteristics 3.1 absolute maximum ratings note: all voltages listed are referenced to ground (0 v, v ss ) except where noted. absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. parameter symbol limit values unit remark min. max. ambient temperature t a 070 c storage temperature t stg C 55 125 c junction temperature t j 125 c soldering temperature t sold 260 c soldering time t sold 10 s input voltage v i C1 7 v output voltage v q C1 7 v dd + 0.5 v v under all conditions at pins xq, out1 3; pins xq, out1 3 supply voltages v dd C1 7 v supply voltage differentials v dd d C 0.25 0.25 v total power dissipation p tot 900 mw esd protection esd C 1 1 kv mil std 883c method 3015.6 100 pf, 1500 w supply pins connected to ground latch-up protection C 100 100 ma except analog outputs, xq
sda 9189x semiconductor group 42 03.96 3.2 operational range parameter symbol limit values unit remark min. typ. max. supply voltages v ddxx 4.75 5 5.5 v ambient temperature t a 02570 c all ttl inputs low-level input voltage v il C 1 0.8 v high-level input voltage v ih 2.0 6 v inset horizontal sync ttl input: hsi 1) horizontal frequency 14.53 16.72 khz signal rise time 15 ns signal high time 100 ns signal low time 900 ns signal setup time 15 ns lh transition of ll3i inset vertical sync ttl input: vsi 1) signal high time 200 ns signal low time 200 ns line locked clock inset picture ttl input: ll3i 1) signal period time 68 80 ns signal rise time 5 ns signal fall time 4 ns signal high time 28 ns signal low time 30 ns 1) all values are referred to the corresponding min ( v ih ) and max ( v il ).
sda 9189x semiconductor group 43 03.96 digital data ttl inputs: yin, uvin 1) signal setup time 15 ns lh transition of ll3i signal hold time 5 ns lh transition of ll3i parent horizontal sync ttl inputs: hsp 1) sync frequency in single-frequency display mode 14.53 16.72 khz quartz frequency 20.48 mhz 15 17.19 khz quartz frequency 21.09 mhz sync frequency in double frequency display mode 29.06 33.44 khz quartz frequency 20.48 mhz 30 34.38 khz quartz frequency 21.09 mhz signal rise time 100 ns noisefree transition signal high time 100 ns signal low time 900 ns parent vertical sync ttl input vsp 1) signal high time 200 ns signal low time 200 ns quartz/ceramic resonator recommended frequency 20.25 20.48 21.3 mhz 21.09 mhz for muse series resistance 10 w c 1 , c 2 33 pf 20 w c 1 , c 2 22 pf 30 w c 1 , c 2 15 pf 40 w c 1 , c 2 10 pf 1) all values are referred to the corresponding min ( v ih ) and max ( v il ). 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9189x semiconductor group 44 03.96 optional ttl clock input: xin 1) clock input cycle time 35 40 ns external line locked 27 mhz clock ( i 2 c: internal pll off) clock input rise time 5 ns clock input fall time 5 ns clock input low time 10 ns clock input high time 10 ns fast i 2 c bus 1) 2) scl clock frequency f scl 400 khz inactive time before start of transmission t buf 1.3 m s setup time start condition t su; sta 0.6 m s hold time start condition t hd; sta 0.6 m s scl low time t low 1.3 m s scl high time t high 0.6 m s setup time data t su; dat 100 ns hold time data t hd; dat 0 0.9 m s sda/scl rise/fall times t r, t f 20 + $ 300 ns $ = 0.1 c b /pf setup time stop condition t su; sto 0.6 m s capacitive load/bus line c b 400 pf 1) all values are referred to the corresponding min ( v ih ) and max ( v il ). 2) this specification of the bus does not have to be identical with the i/o stages specification because of optional series resistors between bus lines and i/o pins. 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9189x semiconductor group 45 03.96 note: in the operational range the functions given in the circuit description are fulfilled. i 2 c bus inputs/output: sda, scl high-level input voltage v ih 3 v dd + 0.5 v also for sda/scl input stages low-level input voltage v il C 0.5 1.5 v spike duration at inputs 0 0 50 ns low-level output current i ol 6ma i 2 c bus three level input adr high-level input voltage v ih 3.5 6 v low-level input voltage v il C 1 0.8 v medium-level voltage v im open input, see chapter 3.3 digital to analog converters (6 bit) out1, out2, out3 full range output voltage v ofr 1 2 v peak to peak reference resistance r ref1 4.2 5.1 6.3 k w no contrast adjustment via i 2 c bus; bits con = 0000 reference resistance r ref2 6.0 6.8 7.5 k w contrast adjustment via i 2 c bus 3.2 operational range (contd) parameter symbol limit values unit remark min. typ. max.
sda 9189x semiconductor group 46 03.96 3.3 characteristics (assuming operational range) parameter symbol limit values unit remark min. max. average total supply current i ddtot 160 ma i ddtot = i dd + i dda note: the maxima do not necessarily coincide. average digital supply current i dd 140 ma average analog supply current i dda 35 ma all digital inputs (ttl, i 2 c) input capacitance c i 7 pf not tested input leakage current C 10 10 m a including leakage current of sda output stage, not pin xin; v =05 v input leakage current C 0.4 0.4 ma pin xin; v =05 v output sel high-level output voltage v oh 2.4 v v dd 1 i oh = C 200 m a selmod = 00 or 01 high-level output voltage v oh 1.5 v v dd 1 i oh = C 4.5 ma selmod = 00 or 01 low-level output voltage v ol 0 0.4 v i ol = 1.6 ma selmod = 00 or 10 low-level output voltage v ol 01v i ol =5ma selmod = 00 or 10 leakage current C 10 a v o =0v v dd output capacitance 7 pf not tested i 2 c bus inputs: sda/scl schmitt trigger hysteresis v hys 0.2 v not tested
sda 9189x semiconductor group 47 03.96 i 2 c bus input/output: sda 1) low-level output voltage v ol 0.4 v i ol =3ma low-level output voltage v ol 0.6 v i ol = max output fall time from min ( v ih ) to max ( v il ) t of 20 + 0.1 c b /pf 250 ns 10 pf c b 400 pf i 2 c bus three-level input adr differential input resistor r in 616k w digital-to-analog converters (6 bit): current source outputs out1, out2, out3 2) d.c. diff. linearity error dle C 0.5 0.5 lsb r ref = 5.1 k w full range output current i o C 1.25 C 1.69 ma v dda = nom, t a = nom, r ref = 5.1 k w , r l = 680 w, after adjustment output voltage ( v o ~ 1.6 v dda r l / r ref ) v o 0.85 1.15 v t a = nom, r l = 680 w r ref = 5.1 k w tracking C 3 3 % v dda = nom, t a = nom, r ref = 5.1 k w , r l = 680 w contrast increase 30 % v dda = nom, t a = nom, r l = 680 w , r ref = 6.8 k w , contrast bits change from 0000 to 1111 1) referenced to scl; open drain output. 2) i 2 c: contrast bits set to zero unless otherwise noted. 3.3 characteristics (contd) (assuming operational range) parameter symbol limit values unit remark min. max.
sda 9189x semiconductor group 48 03.96 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. static digital-to-analog converter (6 bit): analog voltage output anacon d.c. diff. linearity error dle C 1 1 lsb low-level output voltage v ol 0.3 0.7 v r l 3 10 k w high-level output voltage v oh v dda C 0.5 v v dda 1 r l 3 100 k w high-level output voltage v oh v dda C 0.9 v v dda 1 r l 3 10 k w 3.3 characteristics (contd) (assuming operational range) parameter symbol limit values unit remark min. max.
sda 9189x semiconductor group 49 03.96 4 diagrams 4.1 output current of da converters nominal values: v dda =5v; r ref = 5.1 k w ; t =25 c measurements after adjustment via bit d7 of i 2 c bus address 0f for each step note: the output currents are controlled in digital way, so inaccuracy of 1 lsb (ca. 2 %) is always possible. output current = f ( v dda ) output current = f ( t a )
sda 9189x semiconductor group 50 03.96 output current = f ( r ref ) output current = f (con 0 3)
sda 9189x semiconductor group 51 03.96 4.2 application information 4.2.1 application circuit figure 9
sda 9189x semiconductor group 52 03.96 4.2.2 application board layout proposal figure 10 (top view) figure 11 (bottom view)
sda 9189x semiconductor group 53 03.96 4.3 waveforms 4.3.1 phase relation of sync pulses at frame mode figure 12 signal flow of the horizontal synchronization (insert part) figure 13 allowed phase relation of the horizontal/vertical sync pulses (insert channel) if vsidel (0:4) = 0000
sda 9189x semiconductor group 54 03.96 figure 14 allowed phase relation of the horizontal/vertical sync pulses (parent channel) if vspdel (0:4) = 0000
sda 9189x semiconductor group 55 03.96 5 package outlines gps05697 p-dso-32-2 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information dimensions in mm smd = surface mounted device

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